FPGA-Research / FABulous
An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️
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Repository Overview (README excerpt)
Crawler viewFABulous: an Embedded FPGA Framework > [!WARNING] > **Active Development - Use Tagged Releases for Production** > > The **main** branch is under active development and may contain errors, incomplete features, and breaking changes. We are not responsible for any issues caused by using the development branch. > > **For production use, please use tagged releases or reach out to us for further advice.** > > **Documentation:** Our documentation defaults to the latest development version. You can switch between versions (including the latest development version or specific tagged releases) using the version selector at > documentation page. Please ensure you consult the documentation version that matches your installation to avoid compatibility issues. Overview and Features FABulous is an open-source embedded FPGA (eFPGA) framework for generating FPGA fabric and integrates the open source CAD tools Yosys and nextpnr for the user design flow. It is silicon-proven through multiple successful tapeouts across TSMC 180nm, Skywater 130nm, IHP SG13G2, GF180MCU, and 28nm CMOS, FABulous provides a full-stack toolchain from CSV-based fabric definition to production-ready GDSII. The framework supports frame-based partial reconfiguration for runtime reconfiguration of individual FPGA regions. Key Capabilities • **Full-stack toolchain** -- Integrates Yosys (synthesis), nextpnr (place-and-route), and LibreLane (physical design) for a complete fabric-to-GDSII flow. • **CSV-based fabric definition** -- Define custom fabrics through a simple configuration file instead of complex XML architecture descriptions, making customisation accessible to hardware engineers without specialised tooling. • **Modular tile-based architecture** -- Compose fabrics from look-up tables (LUTs), memory blocks, DSPs, I/O blocks, and arithmetic units, with full support for user-defined custom primitives. • **Frame-based partial reconfiguration** -- Supports frame-based partial reconfiguration, enabling runtime reconfiguration of individual FPGA regions without disrupting the rest of the fabric. • **Multi-process-node portability** -- Silicon-proven across 5+ process nodes, demonstrating portability across foundry processes. • **Production-ready GDS flow** -- Generate GDSII layout directly from fabric definitions using the integrated OpenROAD flow, ready for ASIC fabrication. • **Apache 2.0 licence** -- Freely available for both commercial and academic use. Silicon Proven FABulous has been validated through 12+ successful tapeouts across multiple process nodes. | Process Node | Project | Description | | :--- | :--- | :--- | | TSMC 180nm | FORTE-ENG1 | eFPGA with RISC-V core and 1K DPRAM | | Skywater 130nm | STRIVE | 1440 LUT4s + 180 LUT5s + dual-port memories | | Skywater 130nm | Google MPW-2 | CLBs, DSPs, RegFiles, BBRAMs | | Skywater 130nm | Google MPW-3 | FABulous-Sky heterogeneous fabric with custom cells | | Skywater 130nm | Google MPW-3 | FuseRISC -- RISC-V with eFPGA for TensorFlow Micro | | Skywater 130nm | Google MPW-4 | ICESOC -- Ibex-Crypto-eFPGA for cryptography | | Skywater 130nm | Google MPW-4 | ReRAM-based eFPGA | | Skywater 130nm | Google MPW-5 | Full open-source eFPGA with OpenLane | | 130nm / 28nm CMOS | JINST '24 | eFPGA for ML in particle detector readout | | IHP SG13G2 | Greyhound SoC | Taped out, bring-up pending | | IHP SG13G2 | MFPGA | eFPGA on IHP shuttle | | GF180MCU | gf180mcu-fabulous-fpga | eFPGA on wafer.space GF180 run | See the Chip Gallery for detailed descriptions and links to each tapeout. System Requirements To run FABulous, you need Python 3.12 or later. The framework is fully supported on Linux and macOS. Windows users must utilise the Windows Subsystem for Linux (WSL) for compatibility. For the complete toolchain experience, you will need synthesis and place-and-route tools. We recommend installing the OSS CAD Suite, which bundles Yosys and nextpnr, using the provided command. Additionally, using is highly recommended for faster Python package management. Installation You can install FABulous either directly from the Python Package Index for standard usage or from the source code if you intend to contribute to the development of the framework. Standard Installation (via PyPI) Development Installation (from source) Once installed, you can automatically install the recommended CAD tools by running in your terminal. Codespaces and Dev Container (quick use) If you want a pre-configured environment without local dependency setup, you can use the provided container workflows: • **GitHub Codespaces**: open the repository in Codespaces and use the bundled dev container. GUI tools are exposed through a browser VNC session on port . • **Local Dev Container**: open this repository in VS Code and run **Dev Containers: Reopen in Container** with the profile. On Linux, the local profile configures X11 forwarding for GUI tools. For full step-by-step instructions, see the online docs: • Codespaces guide: • Docker and local dev container guide: Using FABulous Interacting with FABulous is typically done via its interactive shell or through automated scripts. The outputs are systematically organised into a directory for generated RTL and a directory for primitive definitions. Bitstreams and logs are stored within your folder. Essential Commands Table | Task | Command | | :---- | :---- | | Create a new project | FABulous create-project \ | | Launch interactive shell | FABulous start | | Run a non-interactive flow | FABulous -p \ run " ; ; ..." | | Execute a TCL script | FABulous -p \ script custom_flow.tcl | | View help documentation | FABulous --help | Typical Interactive Workflow GUI Setup with FABulator FABulator is a companion tool that allows you to visually explore the fabrics generated by FABulous and display user designs. To import a fabric into FABulator, you must first generate a geometry file. You can achieve this by running the following commands within the FABulous shell: *(No…